Send Your Problem
November 13, 2007Being the generous person that I am 
I decided to open a new section in this blog called “Send Your Problem” or SYP.
If you have a design problem of any sort, that you think would interest others, or just that you need help with - send it over - yes, you heard it right. I will try to do the best I can to pick up the most difficult/interesting problems and post them with some solutions (hopefully).
I have limited time, and I really do it on my own spare time so be patient if it takes me time to answer. I will of course, try to address all questions, at least by email.
Hi.I’m working in “Minimizing AES power”.AES is the Advanced Encryption Standard chip.I will be thankful if you have some suggestions specially in kmaps and combinational logic.It is good to say that I’m studying master degree in computer engineering.
Could you please send your problem with specific questions to my private email? nirdahan[at]yahoo[d o t]com like the others did?
Hi Nir,
While doing Static Timing Analysis
is it better to do the analysis with the Pad Ring and IOs included or without the Pad ring and IOS ?
Hi,
I have couple of questions in digital designing as i am new to this. Could you please help me? I Need the answers asap because I am appearing for an interview.
my problems are as below:
1.Using required number of 2:1 MUXs and NOT gates design a logic circuit
to implement the function Z = ( a+b+c) mod 2 where a,b,c are 1 bit numbers
( i.e., Z is the remainder of the operation (a plus b plus c) / 2)
2. A 4-bit serial in Parallel out right shift register with asynchronous preset has
its initial value loaded as (y3y2y1y0= 1101). It is required to generate an output sequence at y3.The desired output sequence at y3 is 110111001000 and it repeats after these twelve bits. Design the combinational logic(ref figure) as
a minimal circuit.
Q3. A 4-bit sequential odd parity checker is to be designed. The input to the circuit is a string of bits. The circuit should check parity of 4 consecutive bits and set the output bit to 1 if the parity is odd. The circuit is in initial state ( S0) when the first bit arrives. The circuit goes back to the initial state after the 4th bit has arrived and start checking the parity for the next 4 bits and the process repeats.
(i) Draw the state diagram ( having not more than eight states)
(ii) Draw the State table
(iii) Design the logic circuit using required number of DFFs and gates.
Looking forward fora positive response.
Thanks in Advance.
hi Ruchi,
these are all interview questions and not design problems! The intent of this section is **not** to help with an interview but to genuinely solve hard design problems.
However, I will try to post some of those questions in the interview problems section.
Ok…thnx..Better if some1 could provide a guidence to solve these questions
Design a combinational circuit, that multiplies an input decimal digit represented in BCD by 5.
The output is to be represented in BCD. Show that the outputs can be obtained from the input lines without using any logic gates.
Hi
If someone could help me in providing me this . it would be realy helpful
Prabir
Parbir,
this is easily solved by looking at all the cases.
the LSB of the result (in BCD) is either 0000 (when the input LSB is 0) or 0101 (when the input LSB is 1).
the MSB of the result is a 0 followed by the 3 MSBs of the input.
to sum up the solution, given the input is [3:0], is:
{”0″,input(3),input(2),input(1)} , {”0″,input(0),”0″,input(0)}
If you still have difficulties with it let me know. we can correspond via email.
it is a nice interview question and I will post it with its solution in the future.
Nir
Hi Nir,
I faced a lot of problem in my last project in which I designed a small 3-stage pipelined CPU. I also used /advance fetch/branch forwarding/stall and instruction cancellation mechanism.
Due to all these, the pipeline becomes hetrogenous (of more than 1 clock cycle) and synchronization is done using valid/stall signals between 2 stages.
It resulted in many combinational loops which were physically present but not functionally. This created a lot of mess during synthesis/STA/BE. We had to manually break these loops as DC was behaving in a very erratic manner, and to maintain timing we had to overconstrain the disabled loop paths.
I would be interested in sharing your opinion about how to handle such cases.
Thanks for your posts,
Deepak