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Adventures in ASIC Digital Design 
Excellent information
Thanks for your help
Please keep doing this excellent work. Apart from technical stuff I also like the way the website is designed. Thanks so much for presenting very useful ideas.
Hi Nir,
What about a Post on “How to avoig Glitches in digital designs”?
I would be interested if you apply any special consideration before simulations. It is clear to me once a glitch is found how to avoid it, but not so clear if you can catch them all before sims (probably not). Obviously, if you look at your “architecture” (I am not sure if you call the schematics this way; I mean a figure with flipflops, gates, logic, etc…) it is easier to find those location where a potential glitch may appear.
regards
José
Hi Nir,
It would be interesting a post on clock generation. It may be more on analog design than digital but I think it has a lot of impact to the digital design. Specially, I would be interested to know how one can generate (digitally?) a clock which is an integer factor bigger in frequency–for instance, three times– than a basis clock (the one given by a ring oscillator or xtal oscillator). Furthermore, it may be important to know how the resulting duty cycle is affected.
Thank you
@jose : As you told I have written an article on how to design a frequency multiplier in my blog.Basically I have implemented the code in VHDL and verified the result in FPGA.
Here is the link to frequency multiplier:
http://vhdlguru.blogspot.com/2010/04/combinatorial-frequency-multiplier.html
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