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Send Your Problem

November 13, 2007

Being the generous person that I am πŸ™‚ I decided to open a new section in this blog called “Send Your Problem” or SYP.

If you have a design problem of any sort, that you think would interest others, or just that you need help with – send it over – yes, you heard it right. I will try to do the best I can to pick up the most difficult/interesting problems and post them with some solutions (hopefully).

I have limited time, and I really do it on my own spare time so be patient if it takes me time to answer. I will of course, try to address all questions, at least by email.

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28 comments

  1. Hi.I’m working in “Minimizing AES power”.AES is the Advanced Encryption Standard chip.I will be thankful if you have some suggestions specially in kmaps and combinational logic.It is good to say that I’m studying master degree in computer engineering.


  2. Could you please send your problem with specific questions to my private email? nirdahan[at]yahoo[d o t]com like the others did?


  3. Hi Nir,

    While doing Static Timing Analysis
    is it better to do the analysis with the Pad Ring and IOs included or without the Pad ring and IOS ?


  4. Hi,
    I have couple of questions in digital designing as i am new to this. Could you please help me? I Need the answers asap because I am appearing for an interview.
    my problems are as below:
    1.Using required number of 2:1 MUXs and NOT gates design a logic circuit
    to implement the function Z = ( a+b+c) mod 2 where a,b,c are 1 bit numbers
    ( i.e., Z is the remainder of the operation (a plus b plus c) / 2)

    2. A 4-bit serial in Parallel out right shift register with asynchronous preset has
    its initial value loaded as (y3y2y1y0= 1101). It is required to generate an output sequence at y3.The desired output sequence at y3 is 110111001000 and it repeats after these twelve bits. Design the combinational logic(ref figure) as
    a minimal circuit.
    Q3. A 4-bit sequential odd parity checker is to be designed. The input to the circuit is a string of bits. The circuit should check parity of 4 consecutive bits and set the output bit to 1 if the parity is odd. The circuit is in initial state ( S0) when the first bit arrives. The circuit goes back to the initial state after the 4th bit has arrived and start checking the parity for the next 4 bits and the process repeats.
    (i) Draw the state diagram ( having not more than eight states)
    (ii) Draw the State table
    (iii) Design the logic circuit using required number of DFFs and gates.
    Looking forward fora positive response.
    Thanks in Advance.


  5. hi Ruchi,

    these are all interview questions and not design problems! The intent of this section is **not** to help with an interview but to genuinely solve hard design problems.
    However, I will try to post some of those questions in the interview problems section.


  6. Ok…thnx..Better if some1 could provide a guidence to solve these questions πŸ™‚


  7. Design a combinational circuit, that multiplies an input decimal digit represented in BCD by 5.
    The output is to be represented in BCD. Show that the outputs can be obtained from the input lines without using any logic gates.


  8. Hi

    If someone could help me in providing me this . it would be realy helpful

    Prabir


  9. Parbir,

    this is easily solved by looking at all the cases.
    the LSB of the result (in BCD) is either 0000 (when the input LSB is 0) or 0101 (when the input LSB is 1).
    the MSB of the result is a 0 followed by the 3 MSBs of the input.

    to sum up the solution, given the input is [3:0], is:
    {“0”,input(3),input(2),input(1)} , {“0″,input(0),”0”,input(0)}

    If you still have difficulties with it let me know. we can correspond via email.
    it is a nice interview question and I will post it with its solution in the future.

    Nir


    • hi nir ,i am not getting wat u r explianing .piz give explanation clearly plz sir


  10. Hi Nir,

    I faced a lot of problem in my last project in which I designed a small 3-stage pipelined CPU. I also used /advance fetch/branch forwarding/stall and instruction cancellation mechanism.
    Due to all these, the pipeline becomes hetrogenous (of more than 1 clock cycle) and synchronization is done using valid/stall signals between 2 stages.
    It resulted in many combinational loops which were physically present but not functionally. This created a lot of mess during synthesis/STA/BE. We had to manually break these loops as DC was behaving in a very erratic manner, and to maintain timing we had to overconstrain the disabled loop paths.

    I would be interested in sharing your opinion about how to handle such cases.

    Thanks for your posts,
    Deepak


  11. Hi nir,
    Can you please answer the first puzzle you posted(regarding xor gates).i could not get the answer for that.


  12. Can you elaborate the answer to prabir sinha’s querie. I could not get it.


  13. Yeah i got the answer for prabir’s question.


  14. Hi Ruchi,

    If still didn’t get the answer for (a+b+c) mod 2 :

    assign a0 = b ? ~c : c;
    assign a1 = b ? c : ~c;
    assign z = a ? a1 : a0;

    Represent the above statements into schematic,


  15. Hi ,
    i am doing the gate level simulation ,since i am getting the setup error at the double registering flop for synchronization . for this problem my senior has recommend to force the D input of the first flip flop and he told me that in real this error wont occur.
    plz just brief me about how it will not be in real scenario .

    Thanks
    manju


  16. Hi, I want to design one one digital: Even Number Counter
    My system will count up from 0 to 30, but only count
    For even number: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, and 28.

    Using seven segment to display the number 0->30 (two seven segment)

    After go to 30, it will count again from 0 until the power is off.

    Only use Flip Flop ICs and logic gates to design this system…

    I dont know how to start this system , anybody can help me to do this system.

    Thanks


  17. design a 4-bit counter! (not 5)
    then connect the LSB to ground (logic 0)
    this will generate a “5 bit” counter which counts only in jumps of 2.

    all that is left is to transfer the binary coded number to the 7 segments


  18. this question was asked in one of my interview.

    if i have ‘n’ boolean variables. how many ‘unique’ Boolean functions i can make out of it?


    • according to Boolean switch function , it’s 2**(2**n)


  19. Hi Nir,
    just i want to ask u one question ,how to implement (x2/16)(in words: X square divided by 16)without using the multiply operator .

    I know how to generate the square of a any number .

    0 + 1 = 1 –> 1square
    1(previous number square ) + 3 = 4 –> 2square
    4(previous number square ) + 5 = 9 –> 3square
    9(previous number square ) + 7 = 4 –> 4square
    …..
    i don’t know how to implement in hardware for X square.

    Thanks
    manju


  20. manju,

    if you want to take the iterative approach and don’t care about run time, you could do what you just describe.
    have one register incremented by 2 in each cycle 1,3,5,7,9…
    and another holding the square value.
    with each cycle add the inc_by_2 register to the previous square value and store it in the square value register itself.

    this could be a neat idea for an interview question.

    Nir


  21. hi nir ,
    thanks for replay.


  22. Hi Nir,
    I want to know how to calculate the Gate count of an chip at the RTL level , then if there any tool is there (ya i know one or two tool are there in the market)then how accurately the tool calculate the gate count without synthesis(without Netlist)of RTL .
    But in conventional way we used to find the area of chip (Digital part) and also the 1x NAND (NOR) gate area .
    using above info ,we used to calculate the gate count in term of Nand gates …..!!!!! but then also its not possible to calculate the exact gate count of an chip . its possible to calculate the exact gate count of a chip .

    Thanks

    manju mandya


  23. HI Nir,

    Is there a methodical way to architecturally model (in C++) an ASIC under development ? How do people model in C++ and run performance analysis on these models to determine feasibility since there is no time concept in C++ ? Should PLI be used ?

    Thanks,

    Raja


  24. I need to know why do we go for modulo addition of numbers, tat too high radix modulo addition.


  25. Design a combinational circuit, that multiplies an input decimal digit represented in BCD by 5. The output is to be represented in BCD. Show that the outputs can be obtained from the input lines without using any logic gates.


  26. What logic implementation iis to be done: for a given variable “rand_a” range which lies from 1 to 1000 will be receiving values randomly , from that what kind of logic implementation can be done to reducing to range from 64 to 100 by another variable say “rand_b” rand_b values must be from 64 to 100
    (hint is u can use arithmetic operation)



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