Challenge #1 – DBI Detect

It has been a while since we had a challenge question on the site (last one was the divide by 3 question), and I would like to have more of those in the future. I will basically pose a problem and ask you to solve it under certain conditions – e.g. least hardware or latency, lowest power etc.

This time the challenge is related to a real problem I encountered recently. I reached a certain solution, which I do not claim to be optimal, actually I have the feeling it can be done better – I am therefore very interested in your own way of solving the problem.

Your challenge is to design a combo-block with 8 inputs and 1 output. You receive an 8-bit vector, If the vector contains 4 ‘1’s or more, the output should be high, otherwise low (This kind of calculation is commonly used for data bus inversion detection).

What is the best way to design it with respect to minimizing latency (in term of delay units), meaning the lowest logic depth possible.

Just so we could compare solutions, let’s agree on some metrics. I am aware that your own library might have different delay ratios between the different elements, but we gotta have something to work with.

Inverter – 1 delay unit

NOR, NAND – 2 delay units

AND, OR – 3 delay units

3 or 4 input NOR, NAND – 4 delay units (2 for first stage + 2 for second stage)

3 or 4 input OR, AND – 6 delay units (2 for first stage + 2 for second stage)

XOR, MUX – 7 delay units (2 AND/OR + 1 Inverter)

Please either post a comment with a detailed solution, or send me an email.

Take it from here guys…