Clock Muxing
May 29, 2007Glitch free clock muxing is tricky. Some designers take it on the safe side and disable both clocks, do the switch and enable the clocks back on. Actually, I do not intend to discuss all the details of glitch-free clock muxing, a nice and very readable article can be found here.
If you finished reading the article above and are back with me, I want you to take a closer look at the second implementation mentioned. Here is a copy of the circuit for your convenience
The key question addressed by the author of the article is what happens if the select signal violates setup and hold conditions on one of the flip-flops? Apparently the flip-flop would go meta-stable and a glitch might occur, right? After all why was the synchronizer introduced in the 3rd circuit on the article. Well take a closer look!!
On closer look we see that both flip-flops operate on the falling edge of the clock, this means that a meta-stable state can occur when the clock is transitioning from a high to a low. But, since after the transition the clock is low, the AND gate immediately after the flop will block the unstable flop value for the entire low period of the clock. Or in other words the meta-stability has the entire low period of the clock to resolve and will not propagate through during this time. Isn’t that absolutely cool??!!
I have to admit that upon seeing this circuit for the first time I missed this point, only after reading one of the application notes at Xilinx it dawned on me. The link can be found here (item #6)
Adventures in ASIC Digital Design 
Hi Nir,
Would you please update the Xilinx application note link or provide the app note title.
Thanks in advance.
Hi Nir,
Nice analysis.
But I wuld like to point out an another issue: metastability do have half cycle to get stable on output path, but how about feedback path (from qn) to other domain flop? In other words, you have half cycle path for metastability to phase-out on one path (output path), but you dont have same amount of time for an another path (feedback path) from qn to other domain flop. Which will lead 2nd flop also to be metastable and which in turn will again make 1st flop metastable and so on, cycle may continue. So, problem will be present without synchronizers! Do let me know your inputs or if my analysis is incorrect.
Thanks,
Jaydip
Hi Nir,
What happens if the Flip-Flop Takes more time than the low period, Because the settling time of the metastable state is dependent on the technology.
Problem will not be solved with the AND gates.
Although it’s an old article, I thought I would post a reply in case someone stumbled upon this page.
2 points here:
* The purpose of the negedge flop is to avoid a clock glitch. Let me call the clock enable signal as EN and the registered enable as regEN. Signal regEN appears at the output of the flop after the flop’s propagation delay. So, when you make EN=0, regEN becomes ‘0’ after tpd. ANDing the clock with this regEN will cause a glitch on the output of the AND gate (and thus the output clock). When you register EN @negedge, EN=0 passes to the output of the flop when the clock is already low. ANDing regEN & CLK now would keep the output clock at 0.
* Now to the interesting point of taking the regEN from a different clock domain to the current clock domain, all you need to do is add another stage of posedge triggered flop before the first flop which actually gives you a 2stage synchronizer for the regEN signal.
well … you do a great job … but i could find any way to write you an e-mail ….
Thanks for the article. Can you update the link of Xilinx app note. The link is not opening.