Dual Edge Binary Counters + Puzzle

June 24, 2009

I lately came across the need to use a dual edge counter, by this I mean a counter which is counting both on the rising and on the falling edge of the clock.
The limitation is that one has to use only normal single edge sensitive flops, the kind you find in each library.

There are several ways to do this, some easier than others. I would like to show you a specific design which is based on the dual edge flop I described in a previous post. This design is just used here to illustrate a point, I do not recommend you use it – there are far better ways. Please refer to the end of the post for more on that.

The figure below depicts the counter:
dual edge counter

The counter is made of 2 n-bit arrays of flops. The one operates on the rising edge, the other on the falling edge. The “+1” logic is calculated from the final XOR output, which is the real output of the counter! The value in each of the n-bit arrays does not represent the true counting value, but is used to calculate the final counter value. Do not make the mistake and use the value directly from either set of flops.

This leads to a small puzzle – given the conditions above, can this counter be done with less flops?


  1. Yes, it’s possible with n flops.
    For each bit of a counter, the toggle frequency is divided by two compared to the previous bit.
    Hence, with a double edge counter, if you consider the n-1 most significant bits, theirs transitions are synchronised only on one edge of the clock. Then, these bits can be done with a regular n-1 bits counter on rising edge.
    The lsb needs to toggle at twice the frequency, which can be done by xor-ing the output of a falling edge toggle flop with the counter lsb.

  2. gee, you are fast!
    very good.
    I hoped to skew people away from the cheaper solution you described, but well done!
    the key observation is that for a binary counter the top n-1 MSBs are toggling at half the frequency and therefore only on a single edge of the clock.
    if we want to keep the condition that we do not introduce data on the clock path, then n+1 flops are needed – (n-1) for the n-1 MSBs + 2 for the LSB.
    The LSB has to toggle with a clock frequency. For the LSB we can use a design similar to the single dual edge flop I described in the previous post.

    good job!


  3. Hi Nir,
    I am late to visit to this blog , but i have read all the posts starting from May 2007 to june 2009 , I can say only one thing no words to appreciate you .. as you said , i will also contribute to this community after i think got some thing to share.

    Krishna Kishore

  4. So Nir,
    how exactly would you code this in rtl ???

  5. There is a problem with the n+1 flops solution.
    If you have the possibility to reset the counter, the clock signal must be in a certain state when the reset is released. If the clock signal is in the other state, the counter will not count correctly.

    The solution with 2n flops does not have this problem.

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