A Coding Tip for Multi Clock Domain Designs

December 13, 2008

Multi clock domain designs are always interesting, but almost always hide some synchronization problems, which are not that trivial. There are tools on the market that identify all(??) clock domain crossings within a design. I personally had no experience with them, so I can’t give an opinion (although I heard some unflattering remarks from fellow engineers).

Seems like each company has its own ways of handling this problem. One of the oldest, easiest and IMHO one of the most efficient ways, is to keep strict naming guidelines for your signals, whether combinatorial or sequential !!

The most common way is to add a prefix to each signal which describes its driver clock e.g. clk_800_mux_32to1_out or clk_666_redge_acknowledge.

If you don’t use this simple technique, you won’t believe how useful it is. Many of the related problems of synchronization are actually discovered during the coding process itself. Moreover, it even makes life easier when doing the code review.

If you have more tips on naming convention guidelines for signals in RTL – post them as a comment!


  1. Hi,
    my 3 cents:
    In addition to your suggestions, most naming schemes which I have seen explicitly indicate whether the signal is low or high active.


  2. In Verilog, I UPPERCASE names for real REGISTERS and LATCHES, lowercase names for combinatorial signals (wire and register types), and CamelCase for Ports and Parameters. Some (older) tools complained, but none lately. It helps!


  3. Maybe it would be a good idea to collect different naming conventions and try to come up with a universal naming guidelines.
    This would be pretty useful – keep’em coming…

  4. Limiting one block to have just one clock domain and not mixing clocks in more than one block. We should try mixing the clock domains in atmost only one block and it would also make reviewing easy. I guess this is a rule of thumb and even today we see IPs not following this simple technique.

  5. To add that one block i was mentioning, should be the synchronization block 🙂

  6. sometimes it doesn’t make sense to separate all clock domains. in many applications where you want to measure or calibrate a PLL or DLL, you usually run 2 (or 3) counters driven by different clocks and have a synchronization scheme that start or stops those counters in a certain way.
    separating this block into 6 different blocks (3 different clock domains + 3 different synchronization blocks) just doesn’t make sense to me.

    sometimes we just have to live with multi clock domain designs.

    in some applications it makes sense though.

  7. With respect to general rtl naming, how would it be if we name a signal by its driver’s name ? Something like sig__.

  8. sig_driverName_pinName

  9. Regarding VHDL, Jiri Gaisler, from Aeroflex Gaisler –www.gaisler.com–, has developed an interesting coding method named the “’two-process’ design method”; which is more than a simple naming convention. See http://www.gaisler.com/doc/vhdl2proc.pdf

    Has anyone experience with this two-process method?

  10. As you said Nir, it is mainly application and scenario dependent and i completely agree. But what i mentioned applies in most trivial cases. A clock generation unit or a reset control unit will surely be an exception as there can be many clock domains and they have to be handled carefully without disintegrating them and for DFT purposes also.

  11. I have never been a big fan of some of the more esoteric naming conventions for HDL code. Like for example using _i and _o for inputs and outputs. In my opinion the editor should be able to figure this out all by itself.

    In some cases it does make sense to use some sort of naming convention, such as using _n to indicate an active low signal.

    I think the reuse methodology manual says that _r should be used for registered signals and this should be another fairly easy thing for the editor to figure out.

    I’m not very happy about naming conventions which require signals to be renamed at many levels of the hierarchy. This makes it harder to follow the signal and harder to write the code as well. (Especially in SystemVerilog where special instantiation modes are available to connect signals to signals of the same name. If you use plain Verilog, verilog-mode for emacs has /*AUTO*/ modes to do the same.)

  12. If any emacs lisp superusers are listening, it would be very cool to have emacs macros in verilog mode that would automate most of the work of signal renaming – i.e. replace all cases of xyz with xyz_r if xyz is assigned in a posedge block, but recognize that abc_r already has _r and don’t make it abc_r_r.

    That can be built upon for naming conventions that would include clock signals, such as _ar/_br if a design has clka and clkb; xyz_r2 for a 1 clock delayed copy of xyz_r, and more.

  13. As an EE student coming from a programming background, I am troubled by the lack of crossover concepts between good programming practice and HDL design. My (just finished) computer architecture class had to work on a Little Computer in VHDL. The lack of a naming convention was apparent and made the work more difficult, e.g. signals named for their source _or_ destination, but not for purpose.

    I have a ton of books on my shelf (Pragmatic Programmer a MUST read) discussing methodologies, patterns, styles, and idioms. Do these ideas exist (or have they been written down) in EE? All I’ve seen so far is mathematics.

    (I’m going to go read the Gaisler paper, now. Thank you!)

  14. Thanks for these great tips.

  15. Wow tha was strange. I just wrote an really long comment but after I clicked submit my comment didn’t show up.
    Grrrr… well I’m not writing all that over again.
    Regardless, just wanted to say superb blog!

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