Another Reason to Add Hierarchies to Your Designs

November 30, 2008

We are usually very annoyed when the team leader insists on code restructuring and hierarchical design.
I also know this very well from the other side as well. Trying to convince designers to better restructure their own design which they know so very well already.

Well, here is another small, yet important reason why you might want to do this more often.
Assume your design is more or less mature, you ran some simulation, went through some synthesis runs and see that you don’t meet timing.
You analyze the timing report just to find a huge timing path optimized by the tool and made of tons of NANDs, NORs, XORs and what not. Well you see the starting point and the end point very clearly, but you find yourself asking if this is the path that goes through the MUX or through the adder maybe?

Most logic designs are extremely complicated and the circuit is not just something you can draw immediately on paper. Moreover, looking at a timing report of optimized logic, it is very hard to interpret the exact path taken through the higher level structured – or in other words, what part of the code I am really looking at here??!! Adding an hierarchy will also add its name to the optimized structures in the timing report and you could then easily pin point your problems.

I even saw an engineer that uses this technique as a debugging tool. If he has a very deep logic cloud, he will intentionally build an hierarchy around say a simple 2:1 MUX in the design and look for it in the timing report. This enables him to “feel” how the synthesis tool optimizes the path and where manual optimization needs to be implemented .

Use this on your bigger blocks, it saves a lot of time and effort in the long run.


  1. Really good tip!
    But wont the design hierarchy result in lesser optimization? Can we optimise the code across hierarchies? I am new to the industry and so not convenient with the tools.

    Thank you

  2. You can easily have your synthesis flatten the entire design.
    In most cases you would actually gain more performance like this.

  3. Hi,
    Nice Blog :). I am new to industry as well. I do agree with you that hierarchy is useful technique in understanding the opti’s done by logic synthesis tool. I think it would really beneficial if there is some kind of verilog to netlist mapping available in the logic synthesis tool.

  4. This helps in functional ECOs quickly in an error-free manner.

  5. Thanks for tips.
    Very good tips for any new comer in IT and any industry.

  6. https://asicdigitaldesign.wordpress.com/category/coding-style/

    Under “Fun With Enable Flip-Flops” , diagram No.5 is the basic gate realization of XOR gate correct?

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