Fun With Enable Flip-Flops

October 27, 2008

Almost each library has enable flip-flops included. Unfortunately, they are not always used to their full potential. We will explore some of their potential in this post.

An enable flop is nothing but a regular flop which only registers new data if the enable signal is high, otherwise it keeps the old value. We normally implement this using a MUX and a feedback from the flop’s output as depicted below.

So what is the big deal about it? The nice thing is that the enable flop is already implemented by the guys who built the library in a very optimized way. Usually implementing this with a MUX before the flop will eat away from the cycle time you could otherwise use for your logic. However, a short glance at your library will prove that this MUX comes almost for free when you use an enable flop (for my current library the cost is 20ps).

So how can we use this to our advantage?

Example #1 – Soft reset coding

In many applications soft reset is a necessity. It is a signal usually driven by a register that will (soft) reset all flip flops given that a clock is running. Many times an enable “if” is also used in conjunction.
This is usually coded in this way (I use Verilog pseudo syntax and ask the forgiveness of you VHDL people):
always @(posedge clk or negedge hard_rst)
if (!hard_rst)
ff <= 1'b0;
else if (!soft_rst)
ff <= 1'b0;
else if (en)
ff <= D;

The above code usually results in the construction given in the picture below. The red arrow represents the critical timing path through a MUX and the AND gate that was generated for the soft reset.

Now, if we could only exchange the order of the last two “if” commands this would put the MUX in front of the AND gate and then we could use an enable flop… well, if we do that, it will not be logically equivalent anymore. Thinking about it a bit harder, we could use a trick – let’s exchange the MUX and the AND gate but during soft reset we could force the select pin of the MUX to be “1”, and thus transferring a “0” to the flop! Here’s the result in a picture form.

We can now use an enable flop and we basically got the MUX delay almost for free. This may look a bit petty to you, but this trick can save you a few extra precious tens or hundreds of pico-seconds.

Example #2 – Toggle Flip Flops

Toggle flops are really neat, and there are many cool ways to use them. The normal implementation requires an XOR gate combining the T input and a feedback of the flop itself.

Let’s have a closer look at the logical implementation of an XOR gate and how it is related to a MUX implementation: (a) is a MUX gate equivalent implementation (b) is an XOR gate equivalent implementation and (c) is an XOR implemented from a MUX.

Now, let’s try making a T flop using an enable flop. We saw already how to change the MUX into an XOR gate – all that is left, is to put everything together.


  1. Hi,
    this slightly off-topic, but I share my thoughts anyways 🙂

    Since I never implemented flip flops with an asynchronous reset using verilog, I was curious why the reset in the sensitivity list is clocked.
    I expected more something of this kind:

    always @(posedge clk or hard_rst)
    if (!hard_rst)
    ff <= 1′b0;
    else if (!soft_rst)
    ff <= 1′b0;
    else if (en)
    ff <= D;

    I found the solution in [1]:

    “Synopsys requires that if any signal in the sensitivity list is edge-sensitive, then all signals in the sensitivity list must be edge-sensitive. In other words, Synopsys forces the correct coding style.
    Verilog simulation does not have this requirement”

    Are there any additional reasons?


    [1] http://ens.ewi.tudelft.nl/Education/courses/et4351/CummingsSNUG2003Boston_Resets.pdf

  2. I think what matters is that a certain coding style is understood by the syntehsis. Even if it would require to state the word pink_elephant before each always describing a flipflop – I wouldn’t have a problem with it, as long as we agree on a certain convention.

  3. I partially agree.
    Firstly, the description language is a tool and not an end in itself. Hence, I agree with your strong dislike on focusing on such.
    Although, it has to be consistent and coherent (no random pink_elephants!). Thus, a language (or synthesis tool) which uses syntactic elements unreasonable is not a well designed one.
    And the negedge in this particular case seems to be unreasonable from a behavioral point of view.


  4. Hi,
    there is a functionnal reason too.

    Without “clocked” reset, when reset is deasserted, the block is executed in simulation. As the reset is deasserted, the first “if” is ignored and the main part of the block is executed. But this behavior is the one wanted on the posedge clock, not on reset deassertion, which leads to a simulation mismatch.

    With “clocked” reset, there are no simulation mismatches.

  5. good point!
    That was the answer that I was looking for… thanks a lot.


  6. I am really confused if “Enable” signal is related to “Clock” pin or “Data” pin. Perhaps I am confusing this with “Clock gating” concept.

    Here are my views:
    The first pic which shows the flipflop with “Enable” pin implementation using MUX, can only control “Data”. For example, if we have a series of registers which share common “clock” and “enable” pins, then using the fig-1 implementation, we will have to replicate the MUX structure at the input of every flipflop.
    Also this might cause the metastability problem if the “Enable” signal changes within the window of the set-up and hold time.

    Instead, if we can
    i) sample the “Enable” signal using a flipflop (This is to make sure we do not allow unwanted change in the “Enable” signal, which can lead to metastability while sampling the actual data.
    ii) multiply the “Enable” flipflop output with clock (using an “AND” gate) and
    iii) clocking all the data flipflops with this clock (i.e, output of “AND” gate).
    The implementation looks something like this:

    I am not sure if the “Clock_Enable” and “Clock_Gating” are discreet concepts. Please correct me if I am wrong.


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