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Max Area = 0 ?

August 24, 2008

You are working on a design, you simulated the thing and it looks promising, first synthesis run also looks clean – jobs done right? wrong!

Many ASIC designers do not care for the area of their blocks. It has to meet the max_transition, max_capacitance and timing requirements but who cares about the area? Well if you are an engineer in soul, you should care.

I completely agree that it is a well accepted strategy not to constrain for area (or max_area = 0) when you first approach synthesis. But this doesn’t mean you should ignore the synthesis area reports, even if die size is not an issue in your project.

Not thinking about the area of your design is definitely a bad habit. Given that your transition, capacitance and timing requirements are met you should aim for lower area for your designs. In many cases the tool will meet the timing requirements at the cost of huge logic duplication and parallelism. This is OK for the critical path, but if you could do better than this for the other paths why not just “help” the tool?

For example, try thinking of pre-scaling wide increment logic or pre-decode deep logical clouds with information that might be available a cycle before. This would add some flip-flops but you might find your area decreasing significantly.

There is almost no design that can’t be improved, sometimes with a lot of engineering effort, but most designs have a lot of low hanging fruits. In my current project, I was working with one of my best engineers on optimizing some big blocks that were a legacy from another designer. In almost all blocks we were able to reduce the overall size by 30% and in some cases by over 50%!! This was not because the blocks were poorly designed, it is just that the previous designer cared less about area issues.

Bottom line – remember that smaller blocks mean:

    – Other blocks are located closer
    – Shorter wires need to be driven through the chip
    – Less hardware
    – Lower power
    – Are just more neat 🙂
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2 comments

  1. Nir,

    It’s really fruitfull to read your blog. And this one is a classical example.

    It would be great if you can compile an aggregated post which enlists a systematic approach to optimization.

    Thanks,
    Anand


  2. hi,
    its interesting while reading, but at the end, i found that it is incomplete, it would have much more interesting if u would have taken some example and how did u reduced the area in that example



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