Arithmetic Tips and Tricks #2 – Another Look at a Slow Adder

August 18, 2008

Do you remember the old serial adder circuit below? A stream of bits comes in (LSB first) on the FA inputs, the present carry-out bit is registered and fed in the next cycle as a carry in. The sum comes in serially on the output (LSB first).

True, it is rather slow – it takes n cycles to add n bits. But hold on, check out the logic depth – one full adder only!! This means the clock can run a lot faster than your typical n-bit adder.
Moreover, it is by far the smallest, cheapest and consumes the least power of all adders known to mankind.

Of course you gotta have this high speed clock available in the system already, and you still gotta know when to stop adding and to sample your result.
Taking all this into consideration, I am sure this old nugget can still be useful somewhere. If you already used it before, or have an idea, place a comment.

One comment

  1. I might argue that it’s not the lowest power, if you look at total power required to perform some n-bit add operation.

    Also, it’s almost a waste to meet setup and handle clk->Q on the flop with so few gates in between.

    One nice variation is to increase the adders used in this approach. You can take 2 bits in, use 2 cascaded full adders. and calculate 2 bits each cycle… or 3, or 4, etc. all the way up to a full n-bit ripple adder at the other extreme. Any of those middle points between 1-bit and n-bit may prove useful.


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