Predictive Synchronizers

July 7, 2008

As we discussed many times before, synchronization of signals involves also latency issues. Sometimes these latency issues are quite a mess. This post will go over the principle of operation of predictive synchronizers, which offer a specific solution for a very specific case.

Let’s start by describing the conditions for this specific case. For the sake of explanation let us assume we have two clock domains with different clock periods. On top we have a certain limited or capped jitter component defined by our spec.
Taking the conservative approach, we would always use a full two flip flop synchronizer. However, a closer look at a typical waveform reveals something interesting.

The figure above shows both clocks. The limited jitter as defined by our spec, is shown in gray. Notice how only during specific periods a full synchronizer needs to be used. For the upper clock each 5th cycle is a “dangerous” one, while for the lower clock each 4th is problematic. The time window in which these danger zones occur is predictable.

In general we could count the clock cycles, and then, when the next clock edge occurs in the “danger zone” we could switch and use a full synchronizer circuit, otherwise a single flop is enough.

A circuit which implements this idea can be seen below. The potentially metastable node is blocked by the FSM during the “danger time” and the synchronizer output is taken, otherwise the normal, first flop’s output, is taken. The logic at the output is basically that of a MUX.


  1. This is a very useful technique. In my last work place we had a guy who wrote scripts that generated all of that automatically just by inserting one clock frequency all the required M/N that must be supported.
    It’s a real hard one to run STA on though. Requires a lot of manual constraints for synthesis and timing analysis.

  2. It must be rather hard to synchronise the state machine with the two clocks. How can it detect where excactly to start counting the cycles to detect the problematic ones?

  3. GIVEN the conditions stated in the post it is actually very easy – it is just a counter.
    Remember the two edge have a “danger zone” any fixed number of cycles. This is not really a completely asynchronous situation.
    The FSM/counter should be in the same clock domain as the received signal – in the above example it should be clocked with the same clock that clocks the blue FF.

  4. ok, but where to start counting? On the dangeruous clock, but how can you detect this in a simple way?

  5. Actually, I’m interested in implementing a similar circuit in IP and I’ve been trying to solve this problem of where to start the counters myself.

    If you assume that both clocks are coming from the same PLL, you may be able to get this phase alignment information from the PLL itself somehow (tho I’m not sure – I don’t know a lot about PLLs.)

    In IP that does not contain the PLL, this is not an option. Here’s one idea:
    – a toggle flop in clock domain #1 (‘1’ in eve cycles, ‘0’ in odd cycles)
    – sample this with 2 flops in clock domain #2. One flop has an intentional hold violation > jitter of both clocks; the other has a meets hold by at least the same value.
    – assuming at least this much margin (sum of the jitters) is available on all other edges, then you know to start your counters on the cycle where the 2 flops sample different values.

    Those 2 flops are probably a nightmare in synthesis and STA, but does this sound like a workable solution?

    Does anyone have any other solutions?

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