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Another FSM Design Tool

April 17, 2008

For those who don’t read through the comments. Harry the ASIC guy commented on the last post about an FSM design environment from Paul Zimmer. You can find more details here.

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2 comments

  1. I just tried this tool for the first time, and it has some promise. There’s a nice separation between the front-end (essentially drawing), and back-end (HDL generation) components. Also, the tool seems flexible enough to generate a wide variety of HDL styles from a single source drawing. (and encompass additional logic that just doesn’t fit into some FSM tools)

    Of course, a strange crash did wipe out my test FSM at around hour 3. I’d recommend using revision control of source files right off the bat.


  2. Hello,

    I know this is the wrong place to place the comments but I wanted to make sure that you read this. I had some questions regarding the self recovery circuit for the Johnson counter.

    Suppose I had a divide by 11 Johnson counter which requires 6 flops. If two bits get flipped, will I have to put additional circuitry to correct for this? I am still a little bit confused about the recovery method. Does correcting for the “010” condition also solve the “0110” condition as well?

    Let’s represent the “0110” as “abcd” then does that mean if we (A OR B) AND (B AND C) and put this into flop D, will this correct the problem?

    When I looked at the spec sheet for a 5 stage Johnson counter, it seemed that they only corrected for the 010 condition and not the 0110 condition. (This is seen here: http://www.nxp.com/acrobat_download/datasheets/HEF4017B_CNV_3.pdf)

    Thanks again for your help,



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