The Principle Behind Multi-Vdd Designs

April 2, 2008

Multi-Vdd design is a sort of buzz word lately. There are still many issues involved before it could become a real accepted and supported design methodology, but I wanted to write a few words on the principle behind the multi-Vdd approach.

The basic idea is that by lowering the operating voltage of a logic gate we naturally also cut the power dissipation through the gate.
The price we pay is that gates operated by lower voltage are somewhat slower (exact factor is dependent on many factors).

The basic idea is to identify the non-critical paths and to power the gates in those paths with a lower voltage. Seen below are two paths, there is obviously less logic through the blue path than through the orange one and is therefore a candidate for being supplied with lower Vdd.


The idea looks elegant but as always the devil is in the details. There are routing overheads for the different power grids, level shifters must be introduced when two different Vdd logic paths converge to create a new logical function, new power source for the new Vdd must be designed and most important of all, there has to be support present by the CAD tools – if that doesn’t exist this technique will be buried.


  1. Hi,
    The issue of routing a separate VDD rail to reduce power in the above mentioned case can be resolved by designing libraries of different gate-channel lengths. For example, if we were designing an ic on 65nm, we can introduce 75nm cells in non-critical paths to reduce power. So, in turn they become multi-vt designs.

  2. notice there is a difference between multi-vt and multi-vdd designs. Multi-vt is another technique used for cutting power.

  3. hi,
    I’d like to ask a question. In TSMC 65nm library cells, the recommend operating voltage is 0.9V–1.26v, then, can I set 0.6V as a low Vdd supply to one islands?

    please refer here http://www.tsmc.com/english/b_technology/b01_platform/b010101_65nm.htm

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