Johnson Counter Recovery Circuits

February 25, 2008

In a previous post I discussed the Johnson counter (diagram below). It was mentioned that if a bit accidentally flips in the wrong place in the counter (due to wrong reset behavior, noise, etc.) it will rotate through the counter indefinitely.


In a robust Johnson counter there is a mechanism for self-correction of these errors. This post discussed in detail how to resolve such single bit errors with minimum hardware overhead.

Let’s assume that for some odd reason within a run of “1”s or “0”s a single bit had flipped. If we now take a snapshot of 3 consecutive bits in the counter as the bits are rotating, we will eventually discover two forbidden states: “010” and “101”. All the other six possible states for 3 consecutive bits are legal – as seen in the table below:


The basic idea, is to try to identify those rogue states and fix them by flipping the middle, erroneous bit and pushing the result to the next state. Naturally, we have to make sure that we keep the normal behavior of the circuit as well.
We will examine two solutions (a) and (b). One more efficient (hardware wise) than the other.

Let’s start with approach (a). With this approach we try to correct both forbidden state. The table bellow shows a snapshot of 3 consecutive bits in the “state” column. One is marked in red the other in orange. The column “next(a)” contains the value to be shifted into the 3rd bit – e.g. if “011” is encountered then the middle “1” will be pushed unchanged to the bit to its right, however if the state “010” will be detected, the middle “1” will be flipped to a “0” and pushed into the right thus correcting a forbidden state.


The second approach (b) corrects only the single forbidden state “010”. Then how come this solves the problem? Approach (b) relies on the fact that state “010” is the inverse state of “101”. It is enough to correct state “010” since state “101” will reach the end of the counter, then will be flipped bit by bit and will eventually appear as “010” in the next cycle through the counter!

The next diagram shows the different hardware implementation for both solutions. While I can be blamed of being petty, solution (b) is definitely cheaper.


The final, self-correcting 4-bit Johnson counter is shown below.


It is important to note that this circuit recovers from a single bit error. If we had a 7-bit Johnson counter and 2 adjacent bits would flip in a middle of a run (unlikely but still possible), we would not detect it with the above circuit. For correcting 2 adjacent flips a wider “snapshot” of 4-bits is needed, and the circuit will naturally become more complex.

It is considered good design practice to have at least a single bit self-correcting circuit, as the one above, for each Johnson counter being used.


  1. Isn’t the circuit in the diagram generating 4-bit sequence?

  2. i do need of “the logic diagram of a divide by 18 Johnson counter and Sketch the
    timing diagram and write the sequence in tabular form.” plz email ne solution for above on priya4sky@rediffmail.com

    • This comment is in reference to the comment by “Priya” above. Are you not ashamed ask for a solution like this? Just asking someone else to do your work!

  3. Hi
    Excellent coverage!!
    Appreciate your good work.

    May I know how states 010 and 101 are the “forbidden states”? Are they because 2 bits flipped? If that is the case, even transition from 011 to 100 is illegal, right?


    • Illegal as they are not in the Johnson Counter Counting Sequence. For a standard 3 bit Johnson Counter, that would be 000,100,110,111,011,001 and back to 000

  4. nice & thanks

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