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Puzzle #8 – Clock Frequency Driver

August 13, 2007

Take the clock frequency circuit I posted about here. As I mentioned the XOR gate at the output might cause some duty cycle distortion with some libraries, due to the fact that most XOR gates are not built to be symmetrical with respect to transition delay.
Now, assume your library has a perfectly symmetrical NAND gate. Could you modify the circuit so the XOR will be replaced by a NAND gate and still have a clock frequency at the output (You are of course allowed to add more logic on other parts of the circuit).

If not, give a short explanation why not. If yes send a circuit description/diagram.

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4 comments

  1. let’s think A is a symmetrical cell too
    A= (P NAND N)
    B=(~P NAND ~N)
    above two items can be implemented by nand gate and inverter,
    then (A NAND B) , add a inverter at last, it’s OK.
    I cannot give a schematic because of no drawing tool, if it’s wrong,pls tell me why. thanks.


  2. […] The clock frequency driver puzzle drew little attention compared to the others and I got only one complete and correct solution for it. What follows is my own solution which I hope will be easily understood. […]


  3. if we have symetric nand gate than I think we only need to covert ex-or gate to nand gate

    and inverter to nand gate also

    p’=(p nand p)

    n’=(n nand n)

    i1=(p’ nand n)

    i2=(p nand n’)

    output=(i1 nand i2)

    here i1 and i2 are internal stages


  4. its awesome question…but i cannot understand the answer..let you explain please..



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