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Driving A Clock Frequency Signal From A Register

August 9, 2007

Usually in semi-custom flows it is a big no-no to use the clock in the data path. Sometimes it is necessary though, to drive a signal with the frequency of the clock to be used in some part of the design or driving it onto a pad. Normally, logical changes occur only on the rising edge of the clock and thus with half the frequency of the clock.

Here is a cool little circuit that will drive a signal which toggles at the clock frequency but is still driven from a register. It is very robust and upon wake up from a reset state will drive a clock like signal with the opposite phase of the clock but with the same frequency. To use the same phase as the clock itself, replace the XOR with an XNOR at the output.

clk_freq_drv1.png

clk_freq_drv2.png

If this circuit should be used as a clock for another block, consider the fact that the XOR gate at the output might introduce duty cycle distortion (DCD) due to the fact that many standard cell library XOR gates do not have a symmetrical behavior when transitioning from a logical 0 to a logical 1 and vice versa.

As an afterthought, it might be interesting to look at the similarities between this circuit and the “Double Edge Flip-Flop” I descried before.

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One comment

  1. […] in ASIC Digital Design Tricks and Tips for ASIC Digital Designers « Driving A Clock Frequency Signal From A Register Puzzle #8 – Clock Frequency Driver August 13th, 2007 Take the clock frequency circuit I […]



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