The Double Edge Flip Flop

July 31, 2007

Sometimes it is necessary to use both the rising and the falling edge of the clock to sample the data. This is sometimes needed in many DDR applications (naturally). The double edge flop is sometimes depicted like that:


The most simple design one can imagine (at least me…), would be to use two flip flops. One sensitive to the rising edge of the clock, the other to the falling edge and to MUX the outputs of both, using the clock itself as the select. This approach is shown below:


What’s wrong with the above approach? Well in an ideal world it is OK, but we have to remember that semi-custom tools/users don’t like to have the clock in the data path. This requirement is justified and can cause a lot of headaches later when doing the clock tree synthesis and when analyzing the timing reports. It is a good idea to avoid such constructions unless they are absolutely necessary. This recommendation applies also for the reset net – try not combining the reset net into your logic clouds.

Here is a cool circuit that can help solve this problem:


I will not take the pleasure from you of drawing the timing diagrams yourself 🙂 and realizing how and why this circuit works, let me just say that IMHO this is a darn cool circuit!

Searching the web a bit I came across a paper which describes practically the same idea by Ralf Hildebrandt. He names it a “Pseudo Dual-Edge Flip Flop”, you can find his short (but more detailed) description, including a VHDL code, here.



  1. If you had double-edge flip flops in a standard cell library, would you use them in your synchronous design — one could reduce the master clock frequency by a factor of two–?

  2. in principle this is correct given that there are no duty cycle issues.
    until now I have always seen some margin being cut due to DCD.
    In General I do believe it a good idea to try to aim for double edge flops and use both edges of the clock, especially when the clock tree takes so much of the power budget, it just looks like pure waste not to use the other edge.

  3. Hi,
    it seems a nice idea… How about area though? Is it a 3x
    for all FFs? And what about the wires shared by these FFs
    and the XOR gates? Dont they also consume a lot power, as
    they alter state in every cycle(worst case) ? Are there
    any power/are results from a real design? Maybe there is
    an area/power tradeoff here…

  4. Pavlos,

    I am sure there are trade off issues involved. This implementation IMITATES a dual edge flop design. I do not say this is how it should be built.
    I am sure that in the transistor level one can do it in a MUCH more efficient way than presented above.

    I am really amazed that standard cell libraries rarely contain cells for dual edge flops. The potential for cutting the frequency in half in a lot of designs is just screaming for their usage.

  5. […] There are several ways to do this, some easier than others. I would like to show you a specific design which is based on the dual edge flop I described in a previous post. […]

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