Some Layout Considerations

July 1, 2007

I work on a fairly large chip. The more reflect on what could have been done better, the more I realize how important floor planning is and how important is the concept work of identifying long lines within the chip and tackling these problems in the architectural planning phase.

The average digital designer will be happy if he finished his HDL coding, simulated it and verified it is working fine. Next he will run it through synthesis to see if timing is OK and job done, right? wrong! There are many problems that simply can’t surface during synthesis. To name a few: routing congestion, cross talk effects and parasitics etc. This post will try concentrate on another issue which is much easier to understand, but when encountering it, it is usually too late in the design to be able to do something radical about it – the physical placement of flip-flops.

The picture below shows a hypothetical architecture of a design, which is very representative of the problems I want to describe.


Flop A is forced to be placed closed to the analog interface at the bottom, to have a clean interface to the digital core. In the same way Flop B is placed near the top, to have a clean interface to the analog part at the top. The signal between them, needs to physically cross the entire chip. The layout tools will place many buffers to have clean sharp edges, but in many cases timing is violated. If this signal has to go through during one clock period, you are in trouble. Many times it is not the case, and pipeline stages can be added along the way, or a multi-cycle path can be defined.
Most designers choose to introduce pipeline stages and to have a cleaner synthesis flow (less special constraints).

The other example shown in the diagram is a register that has loads all over the design. It drives signals in the analog interfaces as well as some state machines in the core itself. Normally, this is not a single wire but an entire bus and pipelining this can be very expensive. In a typical design there are hundreds of registers controlling state machines and settings all over the chip, with wires criss crossing by the thousands. Locating the bad guys should be done as soon as possible.

Some common solutions are:

  1. Using local decoding as described on this post
  2. Reducing the width of your register bus (costs in register read/write time)
  3. Defining registers as quasi-static – changeable only during the power up sequence, static during normal operation
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