Designing Robust Circuits

May 25, 2007

There are many ways to design a certain circuit. Moreover, there are many trade-offs like power, area, speed etc.
In this post we will discuss a bit about robustness and as usual, we will use a practical, real life example to state our point.

When one talks about robustness in digital design, one usually means that if a certain type of failure occurs during operation the circuit does not need outside “help” in order to return to a defined or at least allowed state. Maybe this is a bit cryptic so let’s look at a very simple example – a ring counter.

ring_counter_states.pngAs pictured on the right a 4 bit ring counter has 4 different states, with only a single “1” in each state. “counting” is performed by shifting or more correctly rotating the “1” to one direction with each rising clock edge. Ring counters have many uses, one of the most common is as a pointer for a synchronous FIFO. Because of their simplicity, one finds them many times in high speed full custom designs. Ring counters have only a subset of all possible states as allowed or legal states. For example, the state “1001” is not allowed.

A very simple implementation for a ring counter is the one depicted below. The 4 flip-flops are connected in a circular shift register fashion. Three of the registers have an asynchronous reset pin while the left most has an asynchronous set pin. When going into the reset state the ring counter will assume the state “1000”.


Now, imagine that for some reason (inappropriate reset removal, cross talk noise etc.) the state “1100” appeared in the above design – an illegal state. From now on, the ring counter will always toggle between illegal states and this situation will continue until the next asynchronous reset is de-asserted. If a system is noisy, and such risk is not unthinkable, hard reseting the entire system just to bring the counter to a known state might be disastrous.

Let’s inspect a different, more robust design of a ring counter in the picture below.


With the new implementation the NOR gate is functioning as the left most output. But more important, the NOR gate will drive “0”s into the 3-bit shift register until all 3-bits are “0”, then a “1” will be driven. If we look at a forbidden or illegal state like “0110”, we see that the new circuit will go through the following states: “0110”–>”0011″–>”0001″ until it independently reaches a legal state! This means we might experience an unwanted behavior for a few cycles but we would not need to reset the circuit to bring it back to a legal state.

In a later post, when discussing Johnson counters, we will see this property again.


  1. […] One more interesting point about this implementation is that it does not require reset! The circuit will wake up in some state and will arrive a steady state operation that will generate a divide by 3 clock on its own. We discussed some of those techniques in the past when talking about ring counters – link to that post here. […]

  2. It would be nice if you also explained how from the state transition diagram it can be ensured that for any design , when a bad state is entered a good state is eventually forced. Thanks for this blog. it is a great resource.

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