Comments for Adventures in ASIC Digital Design

Comment on Puzzle #12 – Count and Add in Base -2 by @nks

@nks — Sun, 25 Nov 2012 08:19:42 +0000

yes saini ji ….

Comment on Clock Muxing by johndoe

johndoe — Sun, 25 Nov 2012 05:49:57 +0000

well … you do a great job … but i could find any way to write you an e-mail ….

Comment on Puzzle #12 – Count and Add in Base -2 by saini

saini — Fri, 23 Nov 2012 15:45:03 +0000

Lord ..

Comment on Who’s Writing All This Stuff??? by asaberi2

asaberi2 — Thu, 08 Nov 2012 06:02:40 +0000

Hi Nir;
here is my weblog on “Hacking Cisco hardware interview”
http://alirsaberi.wordpress.com/
I am enjoying ur weblog. Let’s be more in touch
Alan from Montreal

Comment on Puzzle #9 – The Snail – Solution by spacebar24680

spacebar24680 — Thu, 18 Oct 2012 04:02:03 +0000

Code 110010, only 4 bits are needed (since 1100 only occurs forwards and not backwards)

Comment on Send Your Problem by zhuoli

zhuoli — Mon, 15 Oct 2012 01:45:59 +0000

according to Boolean switch function , it’s 2**(2**n)

Comment on Puzzle #5 – Binary-Gray by zhuoli

zhuoli — Wed, 10 Oct 2012 05:50:55 +0000

a small error: the MSB only toggle once if you go through the 2^n counts. so total toggles of binary = 2*2^n – 1

Comment on Clock Muxing by Narmada

Narmada — Mon, 24 Sep 2012 18:35:47 +0000

Although it’s an old article, I thought I would post a reply in case someone stumbled upon this page.
2 points here:
* The purpose of the negedge flop is to avoid a clock glitch. Let me call the clock enable signal as EN and the registered enable as regEN. Signal regEN appears at the output of the flop after the flop’s propagation delay. So, when you make EN=0, regEN becomes ’0′ after tpd. ANDing the clock with this regEN will cause a glitch on the output of the AND gate (and thus the output clock). When you register EN @negedge, EN=0 passes to the output of the flop when the clock is already low. ANDing regEN & CLK now would keep the output clock at 0.
* Now to the interesting point of taking the regEN from a different clock domain to the current clock domain, all you need to do is add another stage of posedge triggered flop before the first flop which actually gives you a 2stage synchronizer for the regEN signal.

Comment on Puzzle #10 – Mux Logic by Gayathri

Gayathri — Fri, 24 Aug 2012 12:09:01 +0000

send me the mux ckt diagrm for diz qn.
my e-mail id- gayathribe93@gmail.com

Comment on Puzzle #8 – Clock Frequency Driver by Job Interview Tips

Job Interview Tips — Fri, 27 Jul 2012 05:07:42 +0000

its awesome question…but i cannot understand the answer..let you explain please..