Comments for Adventures in ASIC Digital Design

Comment on Puzzle #10 – Mux Logic by sravya

sravya — Thu, 29 Oct 2009 04:30:39 +0000

how to design the logic gates using mux? plz give ans

Comment on Low Power Techniques – Reducing Switching by Renjith

Renjith — Wed, 28 Oct 2009 08:44:23 +0000

hi Nir,

Thanks for sharing info about low power techniques.
I had a question about bus inversion. The bus is inverted according to the number of switchings taking place. Could you explain more (or point to a source) as to how exactly this is done. If the bus needs to be inverted, is that decision taken only after realizing how many bits toggle.? in that case transitions already take place. I am not too clear about that part.

thanks
renjith

Comment on Real World Examples #5 – Clock Divider by 5 by Joey

Joey — Wed, 28 Oct 2009 02:09:49 +0000

If flop is allowed, insert a flop on the final output.2 flops are not necessary.

Comment on The Johnson Counter by Troy

Troy — Sat, 17 Oct 2009 03:18:03 +0000

OK, I got it.
http://www.play-hookey.com/digital/johnson_counter.html
Here is an example

Comment on The Johnson Counter by Troy

Troy — Sat, 17 Oct 2009 03:09:19 +0000

“Decoding the state of the counter is extremely easy. A single 2 input gate which detects the border between the “1″s and the “0″s is enough. ”

what this mean? can you give an example?

Comment on Puzzle #2 by Troy

Troy — Wed, 14 Oct 2009 22:04:29 +0000

4 full adders.
bit 1,2,3 into adder1, get s1,c1;
bit 4,5,6 into adder2, get s2,c2;
bit 4,s1,s2 into adder3, get s3,c3;
c1,c2,c3 into adder4, get s4,c4;
c4s4s3 is the final answer.

Comment on Puzzle #1 by Troy

Troy — Wed, 14 Oct 2009 21:48:16 +0000

2 of X and Y to get INV (inputs tied together).
Following 4 outputs tied together (wire-or):
A,B into X, then into INV, get 1st output;
A,B into Y, get 2nd output;
A,~B into X, get 3rd output;
~A,B into X, get 4th output.

Here the output of wire-or is what we get – XOR.

Comment on Real World Examples #5 – Clock Divider by 5 by ao

ao — Wed, 07 Oct 2009 17:01:55 +0000

Recycle counter as D0, D1, D2.

always @(posedge clk)
begin
D0 <= ~(D1 | D2);
D1 <= D0;
D2 <= D1;
end

always @(negedge clk)
begin
D3 <= D2;
end

clk_out = ~(D3 | D2);

Comment on Real World Examples #5 – Clock Divider by 5 by evgeni

evgeni — Wed, 30 Sep 2009 01:14:08 +0000

Clock dividers by 3 and 5 lead to the following question: what’s the simplest circuit that divides a clock by any odd number with 50% duty cycle.

Comment on Puzzle #3 by sudeep

sudeep — Thu, 24 Sep 2009 09:38:56 +0000

solution is

x = x ^ y;
y = x ^ y;
x = x ^ y;

for alu select xor operation, and xnoty 1, 0 , 1 for seleting x y and x as destination register.