Comments on: Dual Edge Binary Counters + Puzzle

By: krishna kishore

krishna kishore — Fri, 24 Jul 2009 10:38:38 +0000

Hi Nir,
I am late to visit to this blog , but i have read all the posts starting from May 2007 to june 2009 , I can say only one thing no words to appreciate you .. as you said , i will also contribute to this community after i think got some thing to share.

Krishna Kishore

By: Nir Dahan

Nir Dahan — Wed, 24 Jun 2009 22:17:34 +0000

gee, you are fast!
very good.
I hoped to skew people away from the cheaper solution you described, but well done!
the key observation is that for a binary counter the top n-1 MSBs are toggling at half the frequency and therefore only on a single edge of the clock.
if we want to keep the condition that we do not introduce data on the clock path, then n+1 flops are needed – (n-1) for the n-1 MSBs + 2 for the LSB.
The LSB has to toggle with a clock frequency. For the LSB we can use a design similar to the single dual edge flop I described in the previous post.

good job!

Nir

By: FLy

FLy — Wed, 24 Jun 2009 22:03:23 +0000

Yes, it’s possible with n flops.
For each bit of a counter, the toggle frequency is divided by two compared to the previous bit.
Hence, with a double edge counter, if you consider the n-1 most significant bits, theirs transitions are synchronised only on one edge of the clock. Then, these bits can be done with a regular n-1 bits counter on rising edge.
The lsb needs to toggle at twice the frequency, which can be done by xor-ing the output of a falling edge toggle flop with the counter lsb.