Comments on: Puzzle #8 – Clock Frequency Driver http://asicdigitaldesign.wordpress.com/2007/08/13/puzzle-8-clock-frequency-driver/ Tricks and Tips for ASIC Digital Designers Tue, 17 Nov 2009 20:00:40 +0000 http://wordpress.com/ hourly 1 By: ankit http://asicdigitaldesign.wordpress.com/2007/08/13/puzzle-8-clock-frequency-driver/#comment-1721 ankit Thu, 14 Aug 2008 17:27:35 +0000 http://asicdigitaldesign.wordpress.com/2007/08/13/puzzle-8-clock-frequency-driver/#comment-1721 if we have symetric nand gate than I think we only need to covert ex-or gate to nand gate and inverter to nand gate also p'=(p nand p) n'=(n nand n) i1=(p' nand n) i2=(p nand n') output=(i1 nand i2) here i1 and i2 are internal stages if we have symetric nand gate than I think we only need to covert ex-or gate to nand gate

and inverter to nand gate also

p’=(p nand p)

n’=(n nand n)

i1=(p’ nand n)

i2=(p nand n’)

output=(i1 nand i2)

here i1 and i2 are internal stages

]]> By: Puzzle #8 - Clock Frequency Driver - Solution « Adventures in ASIC Digital Design http://asicdigitaldesign.wordpress.com/2007/08/13/puzzle-8-clock-frequency-driver/#comment-1518 Puzzle #8 - Clock Frequency Driver - Solution « Adventures in ASIC Digital Design Wed, 26 Mar 2008 16:27:05 +0000 http://asicdigitaldesign.wordpress.com/2007/08/13/puzzle-8-clock-frequency-driver/#comment-1518 [...] The clock frequency driver puzzle drew little attention compared to the others and I got only one complete and correct solution for it. What follows is my own solution which I hope will be easily understood. [...] [...] The clock frequency driver puzzle drew little attention compared to the others and I got only one complete and correct solution for it. What follows is my own solution which I hope will be easily understood. [...]

]]> By: Zhi http://asicdigitaldesign.wordpress.com/2007/08/13/puzzle-8-clock-frequency-driver/#comment-1219 Zhi Mon, 26 Nov 2007 02:40:04 +0000 http://asicdigitaldesign.wordpress.com/2007/08/13/puzzle-8-clock-frequency-driver/#comment-1219 let's think A is a symmetrical cell too A= (P NAND N) B=(~P NAND ~N) above two items can be implemented by nand gate and inverter, then (A NAND B) , add a inverter at last, it's OK. I cannot give a schematic because of no drawing tool, if it's wrong,pls tell me why. thanks. let’s think A is a symmetrical cell too
A= (P NAND N)
B=(~P NAND ~N)
above two items can be implemented by nand gate and inverter,
then (A NAND B) , add a inverter at last, it’s OK.
I cannot give a schematic because of no drawing tool, if it’s wrong,pls tell me why. thanks.

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