The Ultimate Interview Question for Logic Design - A Mini Challenge
July 9, 2007I had countless interviews, with many different companies, large corporations and start ups. For some reason in almost all interviews, which were done in Israel, a single question popped up more often than others (maybe it is an Israeli High-Tech thing…).
Design a clock divide-by-3 circuit with 50% duty cycle
The solution should be easy enough even for a beginner designer. Since this is such a popular question, and since I am getting a decent amount of readers lately, I thought why not make a small challenge - try to find a solution to this problem with minimum hardware.
Please send me your solutions by email - can be found on the about me page.
hi i want solution for ths prob if you can
You need to utilize a combination of positive & negative edge triggered flip flops and a couple of combinational gates.
Hi,
I have two solutions: One that needs two registers but may introduce glitches (bc the clock is used in datapath) and another one that requires 5 in total.
The latter idea is to take a sequence of 6 input clock cycles. Generate two clk/2 clocks (one by using pos. edge triggered FFs and one by using neg. edge triggered FFs) By using the cycle number and the two shifted clock/2 signals i was able to get a glitch free clk/3 output. Any better solution?
I actually used this exercise as a vhdl/testbench example in my internship report for the university
Thx for the inspiration
Philip
[...] getting tons of email with requests to post a solution for this question which was initially posted here. I am going to post now what I consider the “standard minimal solution”, but some of [...]