Comments on: Synchronization of Buses http://asicdigitaldesign.wordpress.com/2007/06/01/synchronization-of-buses/ Tricks and Tips for ASIC Digital Designers Tue, 17 Nov 2009 20:00:40 +0000 http://wordpress.com/ hourly 1 By: Jim Li http://asicdigitaldesign.wordpress.com/2007/06/01/synchronization-of-buses/#comment-1739 Jim Li Thu, 28 Aug 2008 15:56:03 +0000 http://asicdigitaldesign.wordpress.com/2007/06/01/synchronization-of-buses/#comment-1739 Nir, I do not think it is a logical problem. For example, in a data-com design, a transceiver might have a faster sending clock but a slower receiving clock. In that case you still need to capture all the changes and send it out. BTW I like your blogs! Cheers /Jim -------------------- I see you don’t answer… anyways the problem would be if the slow receiver side sees 2 changes. This might not be a synchronization problem (why?) but rather a logical problem. How could the receiver know which bit of the two changed first? Since each single bit change represents a different state, this might through your FSM in wild directions… Nir,
I do not think it is a logical problem.
For example, in a data-com design, a transceiver might have a faster sending clock but a slower receiving clock. In that case you still need to capture all the changes and send it out.
BTW I like your blogs!

Cheers
/Jim

——————–
I see you don’t answer…

anyways the problem would be if the slow receiver side sees 2 changes. This might not be a synchronization problem (why?) but rather a logical problem. How could the receiver know which bit of the two changed first? Since each single bit change represents a different state, this might through your FSM in wild directions…

]]> By: Nir Dahan http://asicdigitaldesign.wordpress.com/2007/06/01/synchronization-of-buses/#comment-1221 Nir Dahan Mon, 26 Nov 2007 09:42:32 +0000 http://asicdigitaldesign.wordpress.com/2007/06/01/synchronization-of-buses/#comment-1221 I see you don't answer... anyways the problem would be if the slow receiver side sees 2 changes. This might not be a synchronization problem (why?) but rather a logical problem. How could the receiver know which bit of the two changed first? Since each single bit change represents a different state, this might through your FSM in wild directions... I see you don’t answer…

anyways the problem would be if the slow receiver side sees 2 changes. This might not be a synchronization problem (why?) but rather a logical problem. How could the receiver know which bit of the two changed first? Since each single bit change represents a different state, this might through your FSM in wild directions…

]]> By: Nir Dahan http://asicdigitaldesign.wordpress.com/2007/06/01/synchronization-of-buses/#comment-1188 Nir Dahan Wed, 21 Nov 2007 16:24:35 +0000 http://asicdigitaldesign.wordpress.com/2007/06/01/synchronization-of-buses/#comment-1188 Lior, imagine the clock on the receiving side is by far slower than the one on the sender side. what will happen on the receive side? Lior,

imagine the clock on the receiving side is by far slower than the one on the sender side.
what will happen on the receive side?

]]> By: Lior Efron http://asicdigitaldesign.wordpress.com/2007/06/01/synchronization-of-buses/#comment-1179 Lior Efron Tue, 20 Nov 2007 15:11:51 +0000 http://asicdigitaldesign.wordpress.com/2007/06/01/synchronization-of-buses/#comment-1179 Nir, Can you explain #2? Thx, Lior Nir,
Can you explain #2?
Thx,
Lior

]]>