Synchronization of Buses
June 1, 2007I know, I know, it is common knowledge that we never synchronize a bus. The reason being the uncertainty of when and how the meta-stability is resolved. You can read more about it in one of my previous posts.
A cool exception of when bus synchronization would be safe, is when you guarantee that:
- On the sender side, one bit only changes at a time – Gray code like behavior
- On the receiver (synchronized bus) side, the sampling clock is fast enough to allow only a single bus change
Just remember that both conditions must be fulfilled.
It is important to note that this can still be dangerous when the sender and receiver have the same frequency but phase is drifting! why???
Are there any other esoteric cases where one could synchronize a bus? comments are welcome!
Nir,
Can you explain #2?
Thx,
Lior
Lior,
imagine the clock on the receiving side is by far slower than the one on the sender side.
what will happen on the receive side?
I see you don’t answer…
anyways the problem would be if the slow receiver side sees 2 changes. This might not be a synchronization problem (why?) but rather a logical problem. How could the receiver know which bit of the two changed first? Since each single bit change represents a different state, this might through your FSM in wild directions…
Nir,
I do not think it is a logical problem.
For example, in a data-com design, a transceiver might have a faster sending clock but a slower receiving clock. In that case you still need to capture all the changes and send it out.
BTW I like your blogs!
Cheers
/Jim
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I see you don’t answer…
anyways the problem would be if the slow receiver side sees 2 changes. This might not be a synchronization problem (why?) but rather a logical problem. How could the receiver know which bit of the two changed first? Since each single bit change represents a different state, this might through your FSM in wild directions…